1. Field of the Invention
This invention relates to semiconductor memories and more particularly to flash EEPROM cells and the method of manufacture thereof.
2. Description of Related Art
Referring to FIG. 2, a fragmentary sectional view of a prior art EEPROM cell 9 is shown. Cell 9 includes a P- substrate 10 with two spaced apart N+ regions in the upper surface of substrate 10. The substrate 10 and N+ regions 17 and 18 are covered with a thin tunnel oxide (silicon dioxide) layer 11. A polysilicon 1 floating gate 12 is formed above and in direct contact with the tunnel oxide layer 11. Above the floating gate 12 is a thin ONO three layer dielectric thin film 14. Above the ONO 14 is formed a blanket polysilicon 2 control gate (word line) layer 26. A control gate (polysilicon 2 word line) layer 16 overlies (traverses) the floating gate 12.
The problem with the device of FIG. 2 is that the tunnel oxide 11 needs to be very thin in order to have sufficient tunneling efficiency. Thin tunnel oxide results in reliability and yield problems.
U.S. Pat. No. 5,101,250 of Arima et al for "Electrically Programmable Non-Volatile Memory Device and Manufacturing Method Thereof" shows a process for forming an EEPROM with a conductive (polysilicon) spacers as floating gates, but no polysilicon oxide, etc.
U.S. Pat. No. 5,108,829 of Manley et al for "Method of Making a Non-Volatile Memory Cell Utilizing Polycrystalline Spacer Tunnel Region" shows a process for forming a polysilicon floating gate extension, which differs from the present invention.